1. Field of the Invention
This invention relates to a phase-locked loop circuit and, more particularly, to a phase frequency detector within a phase-locked loop circuit that imparts hysteresis into a reset signal to avoid dead zone and other non-linear problems associated with conventional phase frequency detectors.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuits are typically used for frequency control. As such, PLL circuits are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. A PLL circuit is often used as a frequency synthesizer, or clock generator. Most clock generators use one or more phase-locked loops to generate one or more different frequencies from one or more reference sources. A reference frequency is usually generated by a reference clock attached to the frequency synthesizer. Ideally, frequency synthesis results in one or more clocking devices that are in phase alignment with the reference clock.
A PLL circuit typically includes four main components: a phase frequency detector (xe2x80x9cPFDxe2x80x9d), a filter, a voltage controlled oscillator (xe2x80x9cVCOxe2x80x9d), and a frequency divider. The PLL circuit is arranged to receive a reference clock signal from a reference source. The phase frequency detector is configured to compare the reference clock signal to a feedback clock signal generated by components within the PLL circuit. In particular, the PFD is configured to detect differences in frequency and/or phase between the reference and feedback clock signals, and to generate compensating xe2x80x9cupxe2x80x9d and xe2x80x9cdownxe2x80x9d signals depending on whether the feedback clock signal is lagging or leading the reference clock signal in frequency or phase. The up/down control signals may be passed through a filter to integrate the control signals into a control voltage, which may be sent to the VCO. The VCO may then convert the voltage information from the up/down control signals into an output signal, which preferably contains frequency and/or phase information. The VCO output signal may be sent back to the PFD via a feedback loop.
In this manner, the PLL circuit is configured to produce a feedback clock signal, which is in phase alignment (i.e. zero phase offset) with the phase of a reference clock signal. If phase alignment is not present, the PFD generates an error signal in the form of the up/down control signals to correct the phase-misalignment. Ideally, the PFD produces an error signal (or, net charge), which is a linear function of the phase offset measured between the reference and feedback signals. As shown in the idealized PFD charge versus phase plot of FIG. 1, a linear relationship may exist between the PFD phase offset and the net charge between about +/xe2x88x922xcfx80 (i.e., +/xe2x88x926.28 radians). A zero net charge may also exist when the phase offset is zero (i.e. when reference and feedback phases are substantially aligned). Thus, the PLL is said to be in frequency and phase xe2x80x9clockxe2x80x9d when operating at zero phase offset, or approximately 0.0 Coulombs (Cb), as shown in FIG. 1.
However, when the two input signals differ in phase by more than about 2xcfx80 radians, the output signal may have a negative net charge when the feedback clock signal occurs more often (i.e., when the feedback clock signal has a higher frequency), and a positive net charge when the reference clock signal occurs more often (i.e., when the reference clock signal has a higher frequency). In this manner, the PFD may deliver a negative net charge, or xe2x80x9cpump downxe2x80x9d pulse, when the feedback clock signal leads the reference clock signal, and a positive net charge, or xe2x80x9cpump upxe2x80x9d pulse, when the feedback clock signal lags the reference clock signal. Therefore, the error signal output from the PFD may drive the system to a zero phase offset even when the frequencies of the reference and feedback clocks are different.
Many conventional PLL circuits suffer from non-ideal characteristics, which may cause the response of an actual PFD circuit to deviate from the ideal response illustrated in FIG. 1. Non-ideal characteristics are illustrated in the non-idealized PHD charge versus phase plot of FIG. 2 and may include, for example, decreased linear range and PFD dead zone. The linear range of the PFD may be defined as the region in which a change in phase results in a linear change in net charge delivered to the PLL. Ideally, the linear range of the PFD extends between about +/xe2x88x922xcfx80, shown as range 10 in FIG. 1. In practice, however, non-zero gate delays and other timing factors may decrease the actual linear range. FIG. 2, for example, illustrates the response of a conventional PFD, which exhibits a decreased linear range extending between approximately +/xe2x88x921.5xcfx80 (represented by range 20). Decreasing the range in which the PFD is monotonic (i.e. linear) may result in a reduced tracking range and pull-in range, and may also increase lock acquisition time. Thus, it may be important to keep the minimum linear range greater than about +/xe2x88x92xcfx80, due to the inability of the PHD to acquire frequency lock within this range, since the net charge will not correspond to the frequency offset. For example, the PFD may generate the wrong direction (i.e. opposite net charge) for more than half of a +/xe2x88x922xcfx80 range if the linear range is less than +/xe2x88x92xcfx80. Preferably, a practical minimum linear range may be about +/xe2x88x924xcfx80/3.
Another problem common to conventional PLL circuits, known as the xe2x80x9cdead zone,xe2x80x9d is illustrated in the non-idealized PFD charge versus phase plot of FIG. 3 as range 30. The dead zone includes a narrow frequency band in a region near the phase lock point (i.e. at zero phase offset). Within this narrow phase region, the reference and feedback signals are so close in phase that there may not be enough time for the PFD corrective output pulses to fully switch so that the charge pump can determine the correct phase error value. Once the phase offset drifts out of this phase region, the PFD may start properly correcting again. However, the dead zone tends to reduce the PLL gain at the phase lock point, and thus xe2x80x9cdeadensxe2x80x9d the response.
The PFD circuits described in early literature appear to attribute the dead zone response, such as that shown in FIG. 3, to large jitter or wandering phases at the lock point. Jitter is a problem common in almost all high-speed synchronous systems, and may occur when a signal deviates in phase or frequency from that of an ideal clock. Jitter, however, may not be the cause of the dead zone problem. The actual cause of the problem may have been previously unknown due to the common misconception that all PLLs had to live with the effects of the dead zone. In an effort to avoid the dead zone, less than desirable fixes were used to reduce the dead zone effects to more tolerable levels. In one example, a current leaking resistor was added to the low pass filter of the PLL circuit to xe2x80x9cpullxe2x80x9d the PLL out of the dead zone. Though the addition of a leakage resistor did result in reducing jitter, it also introduced a large and variable phase offset, which made it difficult to achieve zero phase lock. Thus, the inability of conventional PLL circuits to achieve a zero phase offset with the reference clock signal may be one disadvantage of previous methods.
Therefore, it may be desirable to provide an improved PFD having a response that closely follows an ideal phase offset response. As such, it may be desirable to provide an improved PFD that avoids the dead zone problem, while maximizing the extent of the linear range. It may further be desirable to provide an improved PFD that offers lower power and smaller area than currently available PFDs.
The problems outlined above may be in large part addressed by a PFD, alternatively known simply as a detector, which avoids the dead zone problem while maximizing the linear range and minimizing the power/area concerns of currently available PFDs. As such, the phase frequency detector described herein includes a reset logic gate having a hysteresis input. Including hysteresis in the reset logic gate helps prevent the reset logic gate from switching its output response before corrective output pulses (i.e., pump up and pump down pulses) from the PFD transition to final steady state voltage values.
The phase frequency detector preferably has a linear response at the zero phase offset, or phase lock point, and sustains linearity throughout the entire linear range. In addition, the hysteresis logic gate monitors the corrective output pulses to insert an appropriate amount of time delay into the reset path without introducing additional delay elements. Inappropriate use of delay elements would contribute an arbitrary amount of delay, which may vary with process and could be more than the amount needed by an actual PFD circuit. By including hysteresis in the reset logic gate, however, the linear range of the present PFD is maximized by not taking more delay (or reset time) than is actually needed by the PFD output. Avoiding conventional delay elements (which introduce inappropriate delay amounts) also avoids the additional power consumption of those elements and minimizes the area needed to implement the PFD.
According to one embodiment, a phase frequency detector is described herein as including a first and second latch, where each latch includes a reset input, a clock input, and a pulse output upon which pump up and pump down pulses are produced. In addition, the PFD circuit may include a pair of input conductors adapted to receive a reference clock signal and a feedback clock signal. The reference clock signal may have a reference frequency and phase and the feedback clock signal may have a feedback frequency and phase. As such, a clock input of the first latch may be adapted to receive the reference clock signal, while a clock input of the second latch may be adapted to receive the feedback clock signal. In response to a phase difference between the reference and feedback clock signals, the second latch may generate a first corrective output pulse upon a first output conductor when the phase of the feedback signal xe2x80x9cleadsxe2x80x9d the phase of the reference signal. In this manner, the first output conductor is adapted to receive a pump down signal that transitions to a logic high voltage value if a leading edge of the feedback clock signal precedes a leading edge of the reference clock signal. Alternatively, the second latch may generate a second corrective output pulse upon a second output conductor when the phase of the feedback clock signal xe2x80x9clagsxe2x80x9d the phase of the reference clock signal. Thus, the second output conductor is adapted to receive a pump up signal that transitions to a logic high voltage value if the leading edge of the feedback clock signal follows the leading edge of the reference clock signal.
The PFD may further include a reset path coupled between the first and second output conductors and reset inputs of the first and second latches. Arranged within the reset path is a reset logic gate having hysteresis, which is used to generate a time delay output signal (otherwise referred herein as a xe2x80x9creset signalxe2x80x9d). In this manner, the reset logic gate is coupled to forestall transition of the pump down signal to a logic low voltage value until after the transition of the pump up signal reaches a steady state logic high voltage value for each cycle of the reference clock signal. Alternatively, the logic gate is further coupled to forestall transition of the pump up signal to a logic low voltage value until after the transition of the pump down signal reaches the steady state logic high voltage value for each cycle of the feedback clock signal. Thus, the reset logic gate avoids setting the first and second latches to a reset state until the each of the corrective output pulses substantially reach steady state DC voltage values. As such, the reset logic gate is configured to introduce an appropriate amount of delay without adding delay elements to the reset path of the PFD circuit.
According to another embodiment, a PLL circuit is provided herein. In general, the PLL circuit includes a PFD circuit, which as described above, produces a pump down signal if the detector receives a feedback clock signal before receiving a reference clock signal and forestalls termination of the pump down signal until after a pump up signal achieves a steady state voltage value. In addition, the PFD produces a pump up signal if the detector receives a feedback clock signal after receiving a reference clock signal, and forestalls termination of the pump up signal until after a pump down signal achieves a steady state voltage value. The PLL circuit further includes a charge pump, filter, voltage-controlled oscillator, and feedback frequency divider. The charge pump may be configured to subtract the duration of the pump down signal and the pump up signal and produce a net voltage value that controls the feedback clock signal to match in frequency or phase the reference clock signal. As such, the PLL circuit may receive a reference clock signal from a reference source and may generate an output signal, which may be in phase alignment with the reference clock signal. Optionally, a reference frequency divider may divide the frequency of the reference clock signal to allow the use of higher frequency reference sources or, alternatively, to produce high-frequency phase-locked outputs.
Furthermore, a method for reducing the dead zone of a circuit, which detects a phase or frequency difference between a reference clock signal and a feedback clock signal, is also contemplated. Such a method may include receiving a reference clock signal having a reference clock frequency and phase, and a feedback clock signal having a feedback frequency and phase. The method may also include generating corrective output pulses (i.e., pump up or pump down pulses) depending on whether the feedback clock signal lags or leads, respectively, the reference clock signal. The corrective output pulses may be supplied to a reset logic gate arranged within the reset path of the PFD. The reset logic gate monitors the corrective output pulses and generates a new time delay output signal (i.e., a new reset signal) when the corrective output pulses substantially equal steady state DC voltage values. In this manner, the steady state voltage values of the corrective output pulses are achieved before initiating a reset condition upon a pair of latches that produce the corrective output pulses. Such achieving may impart an amount of delay in the output of the reset logic gate that feeds the reset inputs of the pair of latches. The delay may occur for each cycle of the reference clock signal (when the feedback clock signal lags the reference clock signal) or for each cycle of the feedback clock signal (when the feedback clock signal leads the reference clock signal).